Consider a 1-bit equality comparator with two inputs, i0 and i1, and an output, eq. The eq signal is asserted when i0 and il are equal.
Assume that we want to use basic logic gates, which include not, and, or, and xor cells, to implement the circuit. One way to describe the circuit is to use a sum-of-products format.
The logic expression is
eq = iO . il + iO’ . il’
One possible corresponding VHDL code is shown in Listing 1.1. We examine the language constructs and statements of this code in the following subsections.
Gate-level implementation of a 1-bit comparator
coding Start
=========
library ieee;
use ieee.std-logic-ll64.all;
entity eql is
port (
i0, il: in std-logic;
eq: out std-logic );
end eql;
architecture sop-arch of eql is
signal P0, p1: std-logic;
begin
-- sum of two product terms
eq <= P0 or p1;
-- product terms
p0 <= (not i0) and (not i1);
p1 <= i0 and i1;
end sop-arch ;
========
Coding end
Basic lexical rules
VHDL is case insensitive, which means that upper- and lowercase letters can be used interchangeably, and free formatting, which means that spaces and blank lines can be inserted freely. It is good practice to add proper spaces to make the code clear and to associate special meaning with cases. In this book, we reserve uppercase letters for constants.
An identifier is the name of an object and is composed of 26 letters, digits, and the underscore (-), as in i0, il, and data-busl-enable. The identifier must start with a letter.
The comments start with -- and the text after it is ignored. In this book, the VHDL keywords are shown in boldface type, as in entity, and the comments are shown in italics type, as in
-- this is a comment
Library and package
The first two lines,
library ieee;
use ieee. std-logic-1164, all ;
invoke the std-logic-1164 package from the ieee library. The package and library allow us to add additional types, operators, functions, etc. to VHDL. The two statements are needed because a special data type is used in the code.
Entity declaration
The entity declaration
entity eql is
port (
i0, il: in std-logic;
eq: out std-logic
);
end eql;
essentially outlines the I/O signals of the circuit. The first line indicates that the name of the circuit is eql, and the port section specifies the I/O signals. The basic format for an I/O port declaration is
signal-namel, signal-name2, ... : mode data-type;
The mode term can be in or out, which indicates that the corresponding signals flow “into” or “out of” of the circuit. It can also be inout, for bidirectional signals.
Data type and operators
VHDL is a strongly typed language, which means that an object must have a data type and only the defined values and operations can be applied to the object. Although VHDL is rich in data types, our discussion is limited to a small set of predefined types that are suitable for synthesis, mainly the std-logic type and its variants.
std-logic type The std-logic type is defined in the std-logic-I164 package and consists of nine values. Three of the values, ’ 0 ’ , ’ I ’ , and ’ Z ’ , which stand for logical 0, logical 1, and high impedance, can be synthesized. Two values, ’U’ and ’X’ , which stand for “uninitialized” and “unknown” (e.g., when signals with ’ 0’ and ’ 1 ’ values are tied together), may be encountered in simulation. The other four values, ’ - ’ , ’ H’ , ’ L ’ , and ’ W ’, are not used in this book.
A signal in a digital circuit frequently contains multiple bits. The std-logic-vector
data type, which is defined as an array with elements of std-logic, can be used for this
purpose. For example, let a be an 8-bit input port. It can be declared as
a: in std-logic-vector (7 downto 0) ;
We can use term like a (7 downto 4) to specify a desired range and term like a ( 1) to access
a single element of the array. The array can also be declared in ascending order:
a: in std-logic-vector(0 to 7);
We generally avoid this format since it is more natural to associate the MSB with the leftmost position.
Logical operators Several logical operators, including not, and, or, and xor, are de-
fined over the std-logic-vector and std-logic data type. Bit-wise operation is used
when an operator is applied to an object with the std-logic-vector data type. Note that
the and, or, and xor operators have the same precedence and we need to use parentheses
to specify the desired order of evaluation, as in
(a and b) or (c and d)
Architecture body
The architecture body,
architecture sop-arch of eql is
signal P0, p1: std-logic;
begin
-- sum of two product terms
eq <= P0 or p1;
-- product terms
P0 <= (not i0) and (not il);
p1 <= i0 and il;
end sop-arch
describes operation of the circuit. VHDL allows multiple bodies associated with an entity, and thus the body is identified by the name sop-arch (“sum-of-products architecture”). The architecture body may include an optional declaration section, which specifies constants, internal signals, and so on. Two internal signals are declared in this program:
signal P0, p1: std-logic;
The main description, encompassed between begin and end, contains three concurrent statements. Unlike a program in C language, in which the statements are executed sequen- tially, concurrent statements are like circuit parts that operate in parallel. The signal on the left-hand side of a statement can be considered as the output of that part, and the expression specifies the circuit function and corresponding input signals. For example, consider the statement:
eq <= P0 or p1;
It is a circuit that performs the or operation. When PO or pi changes its value, this statement is activated and the expression is evaluated. The new value is assigned to eq after the default propagation delay.
XILINX FPGA , ALTERA FPGA , SPARTAN , CYCLONE
Assume that we want to use basic logic gates, which include not, and, or, and xor cells, to implement the circuit. One way to describe the circuit is to use a sum-of-products format.
The logic expression is
eq = iO . il + iO’ . il’
One possible corresponding VHDL code is shown in Listing 1.1. We examine the language constructs and statements of this code in the following subsections.
Gate-level implementation of a 1-bit comparator
coding Start
=========
library ieee;
use ieee.std-logic-ll64.all;
entity eql is
port (
i0, il: in std-logic;
eq: out std-logic );
end eql;
architecture sop-arch of eql is
signal P0, p1: std-logic;
begin
-- sum of two product terms
eq <= P0 or p1;
-- product terms
p0 <= (not i0) and (not i1);
p1 <= i0 and i1;
end sop-arch ;
========
Coding end
Basic lexical rules
VHDL is case insensitive, which means that upper- and lowercase letters can be used interchangeably, and free formatting, which means that spaces and blank lines can be inserted freely. It is good practice to add proper spaces to make the code clear and to associate special meaning with cases. In this book, we reserve uppercase letters for constants.
An identifier is the name of an object and is composed of 26 letters, digits, and the underscore (-), as in i0, il, and data-busl-enable. The identifier must start with a letter.
The comments start with -- and the text after it is ignored. In this book, the VHDL keywords are shown in boldface type, as in entity, and the comments are shown in italics type, as in
-- this is a comment
Library and package
The first two lines,
library ieee;
use ieee. std-logic-1164, all ;
invoke the std-logic-1164 package from the ieee library. The package and library allow us to add additional types, operators, functions, etc. to VHDL. The two statements are needed because a special data type is used in the code.
Entity declaration
The entity declaration
entity eql is
port (
i0, il: in std-logic;
eq: out std-logic
);
end eql;
essentially outlines the I/O signals of the circuit. The first line indicates that the name of the circuit is eql, and the port section specifies the I/O signals. The basic format for an I/O port declaration is
signal-namel, signal-name2, ... : mode data-type;
The mode term can be in or out, which indicates that the corresponding signals flow “into” or “out of” of the circuit. It can also be inout, for bidirectional signals.
Data type and operators
VHDL is a strongly typed language, which means that an object must have a data type and only the defined values and operations can be applied to the object. Although VHDL is rich in data types, our discussion is limited to a small set of predefined types that are suitable for synthesis, mainly the std-logic type and its variants.
std-logic type The std-logic type is defined in the std-logic-I164 package and consists of nine values. Three of the values, ’ 0 ’ , ’ I ’ , and ’ Z ’ , which stand for logical 0, logical 1, and high impedance, can be synthesized. Two values, ’U’ and ’X’ , which stand for “uninitialized” and “unknown” (e.g., when signals with ’ 0’ and ’ 1 ’ values are tied together), may be encountered in simulation. The other four values, ’ - ’ , ’ H’ , ’ L ’ , and ’ W ’, are not used in this book.
A signal in a digital circuit frequently contains multiple bits. The std-logic-vector
data type, which is defined as an array with elements of std-logic, can be used for this
purpose. For example, let a be an 8-bit input port. It can be declared as
a: in std-logic-vector (7 downto 0) ;
We can use term like a (7 downto 4) to specify a desired range and term like a ( 1) to access
a single element of the array. The array can also be declared in ascending order:
a: in std-logic-vector(0 to 7);
We generally avoid this format since it is more natural to associate the MSB with the leftmost position.
Logical operators Several logical operators, including not, and, or, and xor, are de-
fined over the std-logic-vector and std-logic data type. Bit-wise operation is used
when an operator is applied to an object with the std-logic-vector data type. Note that
the and, or, and xor operators have the same precedence and we need to use parentheses
to specify the desired order of evaluation, as in
(a and b) or (c and d)
Architecture body
The architecture body,
architecture sop-arch of eql is
signal P0, p1: std-logic;
begin
-- sum of two product terms
eq <= P0 or p1;
-- product terms
P0 <= (not i0) and (not il);
p1 <= i0 and il;
end sop-arch
describes operation of the circuit. VHDL allows multiple bodies associated with an entity, and thus the body is identified by the name sop-arch (“sum-of-products architecture”). The architecture body may include an optional declaration section, which specifies constants, internal signals, and so on. Two internal signals are declared in this program:
signal P0, p1: std-logic;
The main description, encompassed between begin and end, contains three concurrent statements. Unlike a program in C language, in which the statements are executed sequen- tially, concurrent statements are like circuit parts that operate in parallel. The signal on the left-hand side of a statement can be considered as the output of that part, and the expression specifies the circuit function and corresponding input signals. For example, consider the statement:
eq <= P0 or p1;
It is a circuit that performs the or operation. When PO or pi changes its value, this statement is activated and the expression is evaluated. The new value is assigned to eq after the default propagation delay.
XILINX FPGA , ALTERA FPGA , SPARTAN , CYCLONE
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